1. Field of the Invention
This invention relates to a high performance domino STATIC RANDOM ACCESS MEMORY (SRAM) in which the core memory cells are organized into sub-arrays accessed by local bit lines connected to global bit lines, and more particularly to an improved domino SPAM with a local sense amplifier to boost the local bit line voltage during a read operation for cell that has been identified as a slow read cell.
2. Description of Background
A static semiconductor memory typically includes six-transistor cell in which four transistors are configured as a cross-coupled latch for storing data. The remaining two transistors are used to obtain access to the memory cell. During a read access, differential data stored in the memory cell is transferred to the attached bit line pair. A sense amplifier senses the differential voltage that develops across the bit line pair. During a write access, data is written into the memory cell through the differential bit line pair. Typically, one side of the bit line pair is driven to a logic low level potential and the other side if driven to a high voltage level. The cells are arranged in an array that has a grid formed of bit lines and word lines, with the memory cells disposed at intersections of the bit lines and the word lines. The bit lines and the word lines are selectively asserted or negated to enable at least one cell to be read or written to.
As will be appreciated by those skilled in the art, in prior art domino SRAM design the cells are arranged into groups of cells, typically on the order of eight to sixteen cells per group. Each cell in a group is connected to a local bit line pair. The local bit line pair for each group of cells is coupled to a global bit line pair. Rather than use sense amplifier to detect a differential voltage when reading a cell, in a domino SRAM the local bit lines are precharged and discharged by the cell in a read operation, which discharge is detected and determines the state of the cell. The local bit line, the precharge means, and the detection means define a dynamic node of the domino SRAM. Domino SRAMs of the type discussed here are explained in greater detail in U.S. Pat. Nos. 5,729,501, 6,058,065 and 6,657,886, which are incorporated herein by reference.
In a domino SRAM cell, in the read operation the cell must produce a bit line voltage large enough to drive off the SRAM macro with no help from a sense amplifier. This presents a problem because an SRAM typically includes at least a few cells that are “fast to write” but “slow to read”. The problem can occur within the normal process window were the pass gate on one side of the cell is relatively strong (the fast write side) and the pass gate on the other side is relatively weak (the slow read side). The “fast write slow read” cell is not a problem in traditional SRAM designs using a state of the art sense amplifier because if a cell produces 300 mv or 30 mv, the sense amplifier can amplify relatively small bit line voltages. The prior art approach to the problem of a slow read domino SRAM cell is to either swapping in spare bit line columns, or swapping in spare word line rows, or waiting longer for the slow cell to produce the proper voltage needed to drive the SRAM macro. These prior art approaches all result in some form of performance slow down, either fixed or variable.